QpiAI cuts quantum error correction to 1.5 microseconds

QpiAI has introduced a decoder hardware platform for quantum error correction on superconducting systems, reducing correction time on its 64-qubit Kaveri processor to about 1.5 microseconds per cycle.

The work was carried out on QpiAI's Kaveri superconducting quantum processor using compact decoder hardware based on a union-find algorithm. The system reduces error detection and correction time from tens of microseconds with software methods to roughly 1.5 microseconds per correction cycle.

The decoder implements a distance-5 rotated surface code using 49 physical qubits. Each instance runs on a single Kaveri QPU, with one decoder assigned to each chip.

The design is intended to work with existing quantum hardware while reducing reliance on CPUs and GPUs for classical support. It is compatible with superconducting transmon qubits, while separate error-correction methods are being developed for the company's fluxonium-based qubits and distributed system designs.

The project received partial funding from India's National Quantum Mission. Dr Abhay Karandikar, Secretary of the Department of Science and Technology for the Government of India, described the result as a notable step in the country's quantum programme.

"Quantum error correction (QEC) is essential for scalable quantum computing," said Karandikar. "By implementing distance-5 surface code QEC in custom hardware rather than traditional CPUs, QpiAI is accelerating the deployment of its 64-qubit Kaveri QPU in India, marking a major step toward practical, large-scale quantum utility."

Hardware focus

Quantum error correction is widely seen as one of the field's main technical hurdles because quantum states are fragile and prone to noise. Systems must detect and correct errors quickly enough to stay within the qubits' coherence window, or the information is lost before useful computation can be completed.

In QpiAI's implementation, the decoder completes distance-5 surface-code decoding in up to 40 clock cycles. The platform performs five rounds of stabiliser measurements in each cycle, allowing it to detect and correct both qubit and measurement errors.

QpiAI reported coherence figures of about 100 microseconds for T1 and 95 microseconds for T2. On that basis, the decoder can support multiple correction cycles before decoherence becomes a limiting factor.

The current platform can support up to 20 decoders operating in parallel. That would allow simultaneous error correction across multiple logical qubits, which could become increasingly important as systems grow beyond small-scale experimental designs.

QpiAI also highlighted active closed-loop correction, which applies qubit corrections during operation rather than after the fact. The decoder is designed to handle Pauli errors as well as measurement errors in superconducting quantum environments.

Processor design

The Kaveri QPU has qubit connectivity designed for surface-code use, according to QpiAI. Its processor design combines the error-correction architecture with superconducting processor layout and fabrication choices intended to support stabiliser measurement and decoding.

The decoder platform also uses the company's QpiAISense quantum control electronics, supporting broader development work aimed at fault-tolerant quantum computing.

Nagendra Nagaraja, founder and CEO of QpiAI, said the hardware approach offers a route to scaling error correction without the same level of support from general-purpose processors.

"The performance of our new decoder platform demonstrates a practical pathway toward scalable, hardware-accelerated quantum error correction," said Nagaraja. "Compatible with widely used superconducting transmon qubits, the platform limits the need for additional classical support from CPUs and GPUs. QpiAI is also developing next-generation error-correction methods tailored to our own fluxonium-based qubits as well as architectures designed to operate across distributed systems."

The current system has been validated using simulated qubits, with integration and experimental validation on physical qubits under way. The work underscores the focus on custom decoding hardware as quantum computing groups try to move error correction from theory and simulation into working processor environments.