AMD partners with TSMC for 2nm process debut in Venice CPU

AMD has confirmed that its next-generation EPYC central processing unit, codenamed "Venice," is the first high-performance computing silicon in the industry to be brought up on the TSMC 2nm N2 process technology.

The processor, which is scheduled for availability next year, is the result of a partnership between AMD and TSMC to co-optimise new design architectures with advanced process nodes. This announcement represents a significant milestone for AMD's data centre CPU roadmap and demonstrates the ongoing collaboration between the two companies across both technology development and manufacturing expansion.

AMD also revealed that it has successfully brought up and validated its fifth generation EPYC processors at TSMC's fabrication facility in Arizona. According to AMD, this move underpins the company's commitment to US-based semiconductor manufacturing and further geographical diversification of advanced technology production.

Dr. Lisa Su, Chair and CEO of AMD, commented on the partnership's role in the achievement, stating: "TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing. Being a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing."

Dr. C.C. Wei, Chairman and CEO of TSMC, added: "We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab. By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing."

The "Venice" CPU is planned to launch next year, with both companies emphasising the importance of advancing data centre technology through deep engineering and operational alignment. The adoption of TSMC's 2nm process is expected to provide improved performance, enhanced power efficiency, and better production yields for processors manufactured using this node.

AMD's validation of its fifth generation EPYC CPUs at the Arizona fabrication facility highlights a strategic shift towards strengthening domestic supply chains in the United States for advanced semiconductor manufacturing. The expansion into the Arizona site was highlighted by both parties as an example of geographic and technological collaboration in semiconductor production.

AMD stated that its collaboration with TSMC's research and development as well as manufacturing operations has been instrumental in achieving this milestone and underpins its ongoing product development and manufacturing strategies for the data centre segment.

"TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing," said Dr. Lisa Su. "Being a lead HPC customer for TSMC's N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing."

"We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab," remarked Dr. C.C. Wei. "By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing."